Core Knowledge

Learn how to design a simple processor with the RISC-V ISA.
Learn various design techniques used in modern processors, such as out-of-order and cache systems.

Course Requirement

Participants must have digital design knowledge and know how to use Verilog (or VHDL) language.
Participants must be familiar with FPGA work.

Exercises in this course use the Arty-A7 FPGA board. Participants need to have an Arty-A7 to learn this course.
Note: both 35T and 100T versions of the FPGA are ok.

Course List

Lecture Title
1 Introduction
2 RTL Coding
3 Arithmetic
4 Single-Cycle
5 Benchmarking
6 Verification
7 Pipelining
8 Branch Prediction
9 Caches
10 Memory
11 Interconnects
12 Superscalar
13 Out-of-Order
14 Multicore
15 Accelerators

Lecture #1:    Introduction
Description

Lecture #2:    RTL Coding
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Lecture #3:    Arithmetic
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Lecture #4:    Single-Cycle
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Lecture #5:    Benchmarking
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Lecture #6:    Verification
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Lecture #7:    Pipelining
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Lecture #8:    Branch Prediction
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Lecture #9:    Caches
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Lecture #10:    Memory
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Lecture #11:    Interconnects
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Lecture #12:    Superscalar
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Lecture #13:    Out-of-Order
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Lecture #14:    Multicore
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Lecture #15:    Accelerators
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