Core Knowledge

Understand the Very Large-Scale Integration circuit (VLSI) design flow.
Know how to design a Standard Cell (StdCell), then complete a StdCell library for full digital design flow.
Know how to integrate various designs, digital or analog alike, into a FullChip frame.
Design a custom digital integrated circuit using industrial-grade CAD tools.

Course Requirement

Participants must have digital design knowledge and know how to use Verilog (or VHDL) language.

About the PDK:
UEC students will study with the ROHM-180nm process (licensed via VDEC).
Oversea participants will study with the skywater-130nm or openPDK45 processes (open licenses).

About the design tools:
UEC students will practice with a mixed script of Cadence, Synopsys, and Mentor Graphic (licensed via VDEC).
For oversea participants, the oversea partner must provide the tool’s license. Depending on which license the oversea partner has (Cadence or Synopsys, Mentor Graphic or not), we will provide the appropriate script.

Course List

Lecture Title
1 VLSI Introduction
2 MOSFET and Schematic
3 Layout with Virtuoso
4 Standard Cell Library
5 Characterization and Abstraction
6 Synthesis
7 Place and Route
8 Full Digital Design Flow
9 Macro Integration
10 IOs and FullChip Integration
11 Course Summary

Lecture #1:    VLSI Introduction

  • Description:    Introduce the overall VLSI flow and show some VLSI applications. Explain the necessary files when designing circuits. Finally, EDA tools for VLSI design will be introduced.
  • Purpose:         Understand the overall VLSI flow. Distinguish the differences between designing and manufacturing flows. Understand the steps in digital design. Understand what files we need before designing a circuit.

Lecture #2:    MOSFET and Schematic

  • Description:    Briefly review MOSFET characteristics and Boolean functions. Show what needs to be done at the transistor-level optimization. Finally, show how to use tools for schematic design with simulation.
  • Purpose:         Review the basic knowledge about MOSFET and Boolean algebra. Understand how transistor-level optimization is different from logic-gate-level optimization. Know how to use tools for schematic design.

Lecture #3:    Layout with Virtuoso

  • Description:    Introduce the stick diagram method via examples. Provide a guide on using tools to draw a layout of an inverter circuit. Finally, show how to use a tool for design rules check and then run a post-layout simulation with a script.
  • Purpose:         Study the usage of stick diagrams in sketching layouts. Know how to use tools for drawing layout. Know how to check design rules and run post-layout simulations.

Lecture #4:    Standard Cell Library

  • Description:    Introduce the cell-based method and explain the differences between standard and custom cells. Explain the “rules” in standard cell design. Give an example of a standard cell library, then explain each component.
  • Purpose:         Understand the cell-based method, the “rules” when designing a standard cell, the various components in a standard cell library, and which cell type is for which purpose.

Lecture #5:    Characterization and Abstraction

  • Description:    Explain how to create various library files from the original layout. Guide on how to create library files using a characterization tool. Guide on how to create abstract files using an abstraction tool.
  • Purpose:         Know how to use characterization and abstraction tools to create various library files from the original layout.

Lecture #6:    Synthesis

  • Description:    Guide on how to create various library files from the layouts. Guide on using tool for synthesis. Guide on checking the synthesis results.
  • Purpose:         Know how to create necessary files for a Standard Cell (StdCell) library from the existing layouts. Know how to use tools for synthesis.

Lecture #7:    Place and Route

  • Description:    Guide on creating the necessary LEF files. Guide on using tools for Place-and-Route (PnR). Guide on checking the PnR results.
  • Purpose:         Know how to create abstractions (LEF files) for layouts. Know how to use tools for Place-and-Route.

Lecture #8:    Full Digital Design Flow

  • Description:    Explain the completed full digital design flow. Guide on using the full-flow digital design template.
  • Purpose:         Understand the full flow of digital design. Know how to use the full-flow digital design template.

Lecture #9:    Macro Integration

  • Description:    Explain the differences between analog/custom and digital design flows. Show how to manually perform the design rules checks, verifications, and post-layout simulation. Provide a guide on creating other necessary files for FullChip integration.
  • Purpose:         Understand the differences between analog/custom and digital design flows. Know how to manually check the design rules and other verifications on the layout. Finally, know how to create other necessary files for the FullChip integration.

Lecture #10:    IOs and FullChip Integration

  • Description:    Introduce the FullChip integration task and explain the steps. Guide on using the FullChip integration template.
  • Purpose:         Understand the task of FullChip integration and its steps. Know how to use the FullChip integration template.

Lecture #11:    Course Summary

  • Description:    The CMOS characteristics are briefly reviewed, followed by a guide to the schematic and layout with Virtuoso. Then, review all the steps of making a standard cell library and follow up with the detailed digital design flow and FullChip integration flow.
  • Purpose:         Review all lectures related to Advanced VLSI Design course.